Jitter attenuation is utilized where it is desirable to absorb phase variations from an incoming clock, which phase variations result from an imperfect transmission system. These phase variations, if not eliminated, can propagate through a system and cause significant errors. This is especially true in designing devices such as T1 line interface circuits. Typically, these types of devices have a specific jitter requirement associated therewith that must be met by the device manufacturer. Although circuitry presently exists to deal with present day levels of phase variations or jitter on a transmitted clock, this circuitry is generally disposed external to the chip. Increased levels of integration and chip density has mandated the need for new techniques to provide for on-chip jitter attenuators.
One type of jitter attenuation circuit that has been utilized in the industry is an elastic store circuit that absorbs variations in the rate at which data is received. This type of device utilizes a FIFO data register for temporarily storing the incoming data, which data is clocked into the data register by the incoming Write clock. This Write clock, which has undesirable jitter associated therewith, is utilized to increment a Write pointer that determines the location in the FIFO to which data is to be written. A stable Read clock is then generated that drives a Read pointer to output the stored data. Since the jitter is now removed from the incoming data stream, the only jitter present on the output data is that associated with the Read clock. However, it is necessary to insure that the Read clock does not deviate very far from the Write clock, since this will result in the FIFO approaching an underflow or an overflow state, such a state resulting in data errors. Therefore, these type of elastic store circuits utilize some type of control logic circuitry to either speed up the Read clock or slow down the Read clock whenever the FIFO is almost full or almost empty. The phase variations or jitter on the Read clock are therefore a function of this control logic circuitry.